Smartphone passive cooling uses vapor chambers, graphite sheets, and conduction-based heat spreaders to dissipate SoC thermal energy without moving parts. Even Apple's A19 Pro, one of the most efficient flagship chips on the market, ships in the iPhone 17 Pro Max with a vapor chamber to manage its thermal load. The catch is that flagship SoCs sustain 3 to 7 W under continuous gaming or AI workloads, while a smartphone chassis can only shed roughly 6 W before the surface gets uncomfortable to hold. As loads climb, these passive systems approach a physical ceiling defined by wick dry-out and chassis thickness, prompting engineers to look for something that actively moves heat rather than passively spreads it.
|
Key Takeaways • Flagship SoCs sustain 3 to 7 W under continuous load, but a smartphone chassis can only shed roughly 6 W before the surface gets uncomfortable to hold. • Ultra-thin vapor chambers typically cap out below 100 W/cm² before wick dry-out. • Active piezo microfluidic cooling can manage heat flux exceeding 300 W/cm² in form factors as thin as 0.35 mm. • On the bench, a piezo microfluidic film held a 6 W load with a skin temperature of 57.5 °C over the heat source, varying by less than 6 °C across a 70 mm span. • The BOS1931 driver IC consumes 64 mW vs. 695 mW for a comparable analog driver, a 10.8× efficiency gap. |
What is active cooling for smartphones?
Active cooling is a thermal management approach in which a powered mechanism moves a fluid, air or liquid, to extract heat from a source rather than relying on passive conduction and phase change. It has been standard in laptops, gaming consoles, and data center servers for decades.
In smartphones, active cooling has been blocked by three hard constraints: Z-height, power draw, and acoustics. Recent miniaturization is starting to unlock it. RedMagic ships gaming phones with a built-in rotary fan and has demonstrated liquid micropump cooling. Boréas Technologies has developed a piezoelectric liquid micropump platform designed to fit standard smartphone form factors.
This liquid approach, piezo microfluidic cooling, sits at the intersection of microfluidics and semiconductor thermal management, with a growing body of applied research presented at IEEE ITherm and ASME InterPACK.
Common approaches and their limits
Every mainstream cooling approach in smartphones today is passive, meaning its internal heat transport is fundamentally bound by passive limits like solid-state conduction and capillary wick return.
Forced flow through fluidic microchannels completely rewrites this paradigm. By mechanically decoupling fluid velocity from thermal flux, we eliminate the capillary dry-out limits of ultra-thin vapor chambers and collapse localized packaging spreading resistance. As SoC and NPU thermal densities scale up, managing heat transport deterministically, rather than reactively, becomes the only path to sustain maximum clock states.
What does deterministically mean in that context?
|
Approach |
How it works |
Main limitation |
Typical use case |
|
Ultra-thin vapor chambers |
Sealed copper enclosure uses capillary wicking and phase change to spread heat across the chassis. |
Heat flux capped below 100 W/cm² in thin formats; wick dry-out worsens when the device is vertical. |
Flagship smartphones up to ~6 to 7 W sustained SoC load. |
|
Graphite & graphene sheets |
Anisotropic thermal conductors spread heat laterally across the back cover. |
No active heat extraction, only redistribution. Hotspots remain a function of total power. |
Budget devices and complementary spreader layers in flagship designs. |
|
Piezo microfluidic cooling (Boréas approach) |
A piezoelectric micropump driven by a dedicated IC circulates liquid through micro-channels via forced convection, managing heat flux above 300 W/cm² in films as thin as 0.35 mm. |
Requires a sealed liquid loop and custom heat spreader; higher BOM cost vs. passive solutions. |
Sustained high-power SoCs, AI-phones, and devices where venting is off the table. |
How Boréas piezo microfluidic cooling solves this
Our approach drops the vapor chamber and replaces it with a thin polymer film threaded with micro-channels. Inside that film, a piezoelectric micropump pushes liquid through the channels, pulling heat off the SoC footprint and dumping it at an offset zone where there is room to shed it. The BOS1931 drives that pump, and pump speed tracks the SoC's thermal telemetry over I²C in real time, so the loop only spends power when the chip is actually running hot.
Measured thermal performance
We characterized the film on the bench using a 120 by 80 mm, 0.35 mm-thick polymer active cooling film over a 12 by 16 mm heat source. Four thermocouples read the system at once: one in the heat-source core, one on the surface directly above it, and two more out at 20 mm and 70 mm. We then stepped pump state and input power through six phases across roughly 5,500 seconds of continuous running.
Two results matter. The first is how much load the surface absorbs without heating up. With the pump off, the film passively held 1 W at a 57 °C skin temperature; with the pump running, it held 6 W at 57.5 °C. Six times the thermal load, the same surface temperature, because the pump is doing the work the passive film alone cannot.
The second is how even the surface temperature stays. At 6 W with the pump on, the skin read 57.5 °C directly over the source, 58 °C at 20 mm, and 52 °C out at 70 mm, a spread of under 6 °C across the whole panel. Meanwhile, the heat-source core climbed to 94 °C, up from 65.5 °C with the pump off. The internal temperature is high, but the pump spreads that heat so evenly that the user never feels a hot spot. What the system controls is the gradient between the SoC and the skin, not the absolute temperature inside.
Driver IC efficiency
The driver IC is where most of this stands or falls, and it is where the BOS1931 earns its place. Actuating a 10 nF piezo pump at 200 Hz and 190 Vpp from a 3.6 V supply, it pulls 64 mW. We ran a Texas Instruments DRV2667 under the same load and measured 695 mW, roughly 10.8 times as much. On a phone, where the power budget is fought over a milliwatt at a time, that is not a difference you can design around. It is the difference between a cooling loop that pays for itself and one that eats into the budget it was meant to protect.
How an integration works, step by step
- Define your thermal envelope. Target heat flux, available Z-height, and maximum skin temperature determine the film geometry. The Boréas reference design supports integration as thin as 0.35 mm.
- Drive the pump with the BOS1931. The IC (2.1 × 1.7 × 0.625 mm) generates the high-voltage AC waveform required to actuate the piezoelectric pump from a standard battery supply, with SDK-tuned impedance matching to the specific loop geometry.
- Connect via I²C. Pump speed is throttled in real time against SoC thermal telemetry. The host owns the thermal control policy; Boréas provides the drive IC, firmware bridging, and access to qualified piezo actuators through tier-1 manufacturing partners.
A smartphone application example
The following is an illustrative integration scenario based on Boréas reference designs and bench characterization. Specific customer integrations remain confidential.
In a flagship phone, the SoC concentrates its heat into a footprint of roughly 12 by 16 mm, and the back cover has to stay below about 43 to 45 °C wherever a hand touches it. The throttling regime that designers fight today, between 5 and 6 W sustained, is exactly where a passive vapor chamber starts losing the surface. It sheds heat from the area it can reach, but the area directly over the SoC stays hottest, so the limit is set by a single hot spot rather than the whole panel.
Dropping the microfluidic loop into the back-cover stack changes what that panel does. Instead of radiating outward from one point, the pump carries heat off the SoC and rejects it at an offset zone, so the back cover warms more evenly and no single patch runs away. The bench data above shows the consequence: at 6 W the surface varies by only a few degrees from directly over the source out to 70 mm away, even as the core climbs to 94 °C. For the OEM that means the thermal budget is set by the average skin temperature across the cover, not by the worst point under a thumb, and it comes in a 0.35 mm stack that draws 64 mW to run.
Customer integrations and measured results under specific OEM constraints are available under NDA. Contact info@boreas.ca.
Frequently asked questions
Why do smartphones overheat under sustained gaming or AI workloads?
Flagship SoCs sustain 3 to 7 W under continuous gaming or AI workloads, but a phone chassis can only shed roughly 6 W before the surface gets uncomfortable to hold. Vapor chambers and graphite sheets spread heat passively, but with limited efficiency under sustained load. The whole device acts as a heat sink, and surface temperatures climb until the chip throttles itself to protect the silicon.
What is the difference between passive and active smartphone cooling?
Passive cooling moves heat without any powered mechanism, using vapor chambers, graphite sheets, or thermal interface materials. Active cooling adds a powered element such as a piezoelectric pump or MEMS fan that mechanically moves a cooling fluid. Active systems extract heat from a localized source and carry it to colder areas of the device; passive systems can only redistribute it, so hotspots persist.
Can a liquid-cooled smartphone leak?
A properly engineered piezo microfluidic loop is sealed and contains no rotating seals or external ports. The working fluid is hermetically enclosed and the piezoelectric pump has no rotary moving parts. Because each design is device specific, long-term reliability still requires validation against drop, vibration, and thermal-cycle stress profiles defined by the OEM's qualification standards.
How thin can active liquid cooling be made for smartphones?
Active piezo microfluidic systems have been demonstrated in polymer cooling films as thin as 0.35 mm, below the 0.4 to 0.6 mm typical of ultra-thin vapor chamber assemblies. Thinness is achievable because flow rate, not internal vapor volume, governs heat capacity. The system scales with fluid velocity rather than chassis thickness.
How much power does a piezo cooling system consume?
A piezo micropump driver such as the BOS1931 consumes approximately 64 mW driving a 10 nF pump at 200 Hz and 190 Vpp. Total system power depends on pump duty cycle, which is typically a small fraction of the SoC power being managed, so net device efficiency can improve when cooling prevents throttling.
Glossary
Vapor chamber: A flat, sealed heat spreader containing a wick and working fluid that transfers heat via evaporation and condensation.
Heat flux: Thermal power transferred per unit area, measured in watts per square centimeter (W/cm²).
TDP (Thermal Design Power): The maximum sustained heat output a chip can generate, expressed in watts.
Wick dry-out: The failure mode in vapor chambers when capillary action can no longer return liquid to the evaporator zone, collapsing thermal performance.
Related reading
BOS1931 piezo driver IC specifications
Boréas piezo microfluidic cooling for mobile devices
How CapDrive® technology reduces driver power consumption
Evaluate Boréas piezo drivers with our development kits
Integration SDK and documentation for OEM design teams
Next steps
See the Boréas microfluidic cooling solution overview → https://www.boreas.ca/pages/micropump-liquid-cooling
Discuss your thermal design with our applications engineering team → info@boreas.ca
Request the BOS1931 datasheet and microfluidic cooling design guide → https://www.boreas.ca/pages/bos1921-kit-technical-documentation
About the author
Marc-André Morin, Marketing, Communication & Distribution Manager — Boréas Technologies.
Leave a comment